 `timescale 1ns/1ps
module top_module();
    // Inputs
    reg [31:0] a;
    reg [31:0] b;
    
    // Outputs
    wire [31:0] c;
    wire err;
    
    // Instantiate the Unit Under Test (UUT)
    ieee754_multi uut (
        .a(a),
        .b(b),
        .c(c),
        .err(err)
    );
    
    // Test procedure
    initial begin
        // Dump waveform
        $dumpfile("wave.vcd");
        $dumpvars(0, top_module);
        
        $display("========= IEEE754 Multiplier Test =========");
        
        // Test Case 1: 1.0 * 1.0
        a = 32'h3F800000; // 1.0
        b = 32'h3F800000; // 1.0
        #10;
        $display("Test1: 1.0 * 1.0 -> c=%h, err=%b | %s",
                 c, err,
                 (c == 32'h3F800000 && err == 0) ? "PASS" : "FAIL");
        
        // Test Case 2: 2.0 * 2.0
        a = 32'h40000000; // 2.0
        b = 32'h40000000; // 2.0
        #10;
        $display("Test2: 2.0 * 2.0 -> c=%h, err=%b | %s",
                 c, err,
                 (c == 32'h40800000 && err == 0) ? "PASS" : "FAIL");
        
        // Test Case 3: Negative multiplication
        a = 32'hBF800000; // -1.0
        b = 32'h40000000; // 2.0
        #10;
        $display("Test3: -1.0 * 2.0 -> c=%h, err=%b | %s",
                 c, err,
                 (c == 32'hC0000000 && err == 0) ? "PASS" : "FAIL");
        
        // Test Case 4: Underflow
        a = 32'h00000001; // 最小非规格化数
        b = 32'h00000001; 
        #10;
        $display("Test4: Underflow -> c=%h, err=%b | %s",
                 c, err,
                 (c == 32'h00000000 && err == 1) ? "PASS" : "FAIL");
        
        // Test Case 5: Overflow
        a = 32'h7F000000; // 大数
        b = 32'h7F000000; 
        #10;
        $display("Test5: Overflow -> c=%h, err=%b | %s",
                 c, err,
                 (c == 32'h7F800000 && err == 1) ? "PASS" : "FAIL");
        
        // Test Case 6: 1.5 * 1.5
        a = 32'h3FC00000; // 1.5
        b = 32'h3FC00000; // 1.5
        #10;
        $display("Test6: 1.5 * 1.5 -> c=%h, err=%b | %s",
                 c, err,
                 (c == 32'h40100000 && err == 0) ? "PASS" : "FAIL");
        
        $display("========== Test Completed ==========");
        #10 $finish;
    end
endmodule
